Philips Semiconductors
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
Product data
87LPC767
500 kHz
R/C OSCILLATOR
CLOCK OUT
ENABLE
WDCLK * WDTE
STATE CLOCK
WDTE + WDRUN
WDS2–0
(WDCON.2–0)
8 TO 1 MUX
8 MSBs
20-BIT COUNTER
CLEAR
WATCHDOG
RESET
WATCHDOG
INTERRUPT
WDTE (UCFG1.7)
WATCHDOG
FEED DETECT
BOD (xxx.x)
POR (xxx.x)
Figure 35. Block Diagram of the Watchdog Timer
S
Q
R
WDOVF
(WDCON.5)
SU01182
WDCON Address: A7h
Not Bit Addressable
Reset Value: S 30h for a watchdog reset.
S 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
S 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
7
6
5
4
3
2
1
0
—
— WDOVF WDRUN WDCLK WDS2 WDS1 WDS0
BIT
SYMBOL
WDCON.7, 6 —
WDCON.5 WDOVF
WDCON.4 WDRUN
WDCON.3 WDCLK
WDCON.2–0 WDS2–0
WDS2–0
000
001
010
011
100
101
110
111
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
Watchdog rate select.
Timeout Clocks Minimum Time
Nominal Time
Maximum Time
8,192
10 ms
16 ms
23 ms
16,384
20 ms
32 ms
45 ms
32,768
41 ms
65 ms
90 ms
65,536
82 ms
131 ms
180 ms
131,072
165 ms
262 ms
360 ms
262,144
330 ms
524 ms
719 ms
524,288
660 ms
1.05 sec
1.44 sec
1,048,576
1.3 sec
2.1 sec
2.9 sec
SU01183
Figure 36. Watchdog Timer Control Register (WDCON)
2001 Aug 07
45