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MS81V06160-XXTA View Datasheet(PDF) - Oki Electric Industry

Part NameMS81V06160-XXTA OKI
Oki Electric Industry OKI
Description(401,408-word × 16-bit) FIFO memory
MS81V06160-XXTA Datasheet PDF : 18 Pages
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Semiconductor
MS81V06160
PIN DESCRIPTION
Data Inputs: (DI0-15)
These pins are used for serial data inputs.
Write Reset: RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS8106160 is in fully static operation as long as the power is on. Note that WE setup and
hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 2.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 2.
Data Out: (DO0-15)
These pins are used for serial data outputs.
Read Reset: RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address pointers to zero.
RSTR setup and hold times are referenced to the rising edge of SRCK.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
The latency for the read operation control by RE is 2. After read reset, RE must remain low for more than 1600 ns
(tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought
high.
After read reset, RE should be remained high for 2 cycles after driving RE high first.
Output Enable: OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced
to the rising edge of SRCK. The latency for the read operation control by OE is 2.
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