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MS81V06160-15TA View Datasheet(PDF) - Oki Electric Industry

Part NameMS81V06160-15TA OKI
Oki Electric Industry OKI
Description(401,408-word × 16-bit) FIFO memory
MS81V06160-15TA Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
Semiconductor
MS81V06160
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK
cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that
the first field will still be read out. The first field of data that is read out while the second field of data is written is
called “old data”. In order to read out “new data”, i.e., the second field written in, read reset must be input after
write address 200 the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles.
If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out
will be undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such a timing
should be avoided.
When the read address delay is between more than 71 and less than 599 or more than 401,408, read data will be
undetermined. However, normal write is achieved in this address codition.
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