OR2T06A-3BC144I View Datasheet(PDF) - Unspecified
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OR2T06A-3BC144I Datasheet PDF : 192 Pages
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Data Sheet
June 1999
ORCA Series 2 FPGAs
Description
The ORCA Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest ORCA series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
ments for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and tempera-
ture ranges.
The ORCA series FPGA consists of two basic ele-
ments: programmable logic cells (PLCs) and program-
mable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC
contains a programmable function unit (PFU). The
PLCs and PICs also contain routing resources and
configuration RAM. All logic is done in the PFU. Each
PFU contains four 16-bit look-up tables (LUTs) and four
latches/flip-flops (FFs).
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and ver-
tical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
Some examples of the resources required and the per-
formance that can be achieved using these devices are
represented in Table 2.
Table 2. ORCA Series 2 System Performance
Function
#
PFUs
16-bit loadable up/down
4
counter
16-bit accumulator
4
8 x 8 parallel multiplier:
— Multiplier mode, unpipelined1 22
— ROM mode, unpipelined2
9
— Multiplier mode, pipelined3
44
32 x 16 RAM:
— Single port (read and write/
9
cycle)4
— Single port5
9
— Dual port6
16
36-bit parity check (internal)
4
32-bit address decode
3.25
(internal)
-2A
51.0
51.0
14.2
41.5
50.5
21.8
38.2
38.2
13.9
12.3
-3A
66.7
66.7
19.3
55.6
69.0
28.6
52.6
52.6
11.0
9.5
-4A
87.0
Speed Grade
-5A -6A
104.2 129.9
-7A
144.9
-7B
131.6
-8B
149.3
Unit
MHz
87.0 104.2 129.9 144.9 131.6 149.3 MHz
25.1
71.9
82.0
31.0
87.7
103.1
36.0
107.5
125.0
40.3
122.0
142.9
37.7
103.1
123.5
44.8
120.5
142.9
MHz
MHz
MHz
36.2 53.8 53.8 62.5 57.5 69.4 MHz
69.0 92.6 92.6 96.2 97.7 112.4 MHz
83.3 92.6 92.6 96.2 97.7 112.4 MHz
9.1
7.4
5.6
5.2
6.1
5.1
ns
7.5
6.1
4.6
4.3
4.8
4.0
ns
1. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
tiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
7. OR2TxxB available only in -7 and -8 speeds only.
8. Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Lucent Technologies Inc.
3
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