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OR2T06A-3S84I View Datasheet(PDF) - Unspecified

Part NameOR2T06A-3S84I ETC
Unspecified 
DescriptionORCA® Series 2 Field-Programmable Gate Arrays


OR2T06A-3S84I Datasheet PDF : 192 Pages
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Data Sheet
June 1999
ORCA® Series 2
Field-Programmable Gate Arrays
Features
s High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
s High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
s Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
s Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
s Eight 3-state buffers per PFU for on-chip bus structures
s Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
s Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
s Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
s Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
s Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
Table 1. ORCA Series 2 FPGAs
s Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
s Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
s Pinout-compatible with new ORCA Series 3 FPGAs
s TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
s Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
s Built-in boundary scan (IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
s Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
s Full PCI bus compliance for all devices
s Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ORCA Foundry
Development System support (for back-end implementa-
tion)
s New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
# LUTs Registers
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
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Description
The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources.
The Series 2 devices can be used as drop-in replace ments for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each other. The usable gate counts associated with each series are provided in Table 1. Both series are offered in a variety of packages, speed grades, and temperature ranges.

 

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