NB3N551DG View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
NB3N551DG Datasheet PDF : 7 Pages
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NB3N551
Table 1. OE, OUTPUT ENABLE FUNCTION
OE
Function
0
Disable
1
Enable
Table 2. PIN DESCRIPTION
Pin #
Name
Type
Description
1
ICLK
(LV)CMOS/(LV)TTL Input Clock Input. Internal pull-up resistor.
2
Q1
(LV)CMOS/(LV)TTL Output Clock Output 1
3
Q2
(LV)CMOS/(LV)TTL Output Clock Output 2
4
Q3
(LV)CMOS/(LV)TTL Output Clock Output 3
5
Q4
(LV)CMOS/(LV)TTL Output Clock Output 4
6
GND
Power
Negative supply voltage; Connect to ground, 0 V
7
VDD
Power
Positive supply voltage (3.0 V to 5.5 V)
8
OE
(LV)CMOS/(LV)TTL Input Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pull−up resistor. Three−states outputs when LOW.
−
EP
Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
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