MX10EXA
ALE
tLLWL
tWLWH
WRL or WRH
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
tAVLL tLLAX
tQVWX
A4-A11 or A4-A15
tAVWL
DATA OUT*
A0 or A1-A3, A12-19
tWHQX
tUAWH
* INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits).
Figure 24. External Data Memory Write Cycle
XTAL1
ALE
tCRAR
ADDRESS BUS
WAIT
BUS STROBE
(WRL,WRH,
RD,OR PSEN)
tWTH
tWTL
(The dashed line shows the strobe without WAIT.)
Figure 25. WAIT Signal Timing
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
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