MX10EXA View Datasheet(PDF) - Macronix International
Part Name
Description
Manufacturer
MX10EXA Datasheet PDF : 55 Pages
| |||
MX10EXA
SYMBOL FIGURE
Data Write Cycle
tWLWH
24
tLLWL
24
tQVWX
24
t
24
WHQX
tAVWL
24
tUAWH
24
Wait Input
tWTH
25
tWTL
25
PARAMETER
VARIABLE CLOCK
MIN
MAX
UNIT
WR pulse width
(V8 * tC)-10
ns
ALE falling edge to WR asserted
(V12 * tC)-10
ns
Data valid before WR asserted (data setup time) (V13 * tC)-22
ns
Data hold time after WR de-asserted (Note 6)
(V11 * t )-5
ns
C
Address valid to WR asserted (address setup time) (V9 * tC)-22
ns
(Note 5)
Hold time of unlatched part of address after WR (V11 * tC)-7
ns
is de-asserted
WAIT stable after bus strobe
(RD,WR,or PSEN) asserted
WAIT hold after bus strobe
(RD,WR,or PSEN) asserted
(V10*tC)-30 ns
(V10 * tC)-5
ns
NOTES:
1.Load capacitance for all outputs = 80p F.
2.Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers
(BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL
register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits
or the CRAl, CRA0, and ALEW bits in the BTRL register.
- For a bus cycle with no ALE, V2 = l if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that
during burst mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies
for the purpose of determining peripheral timing requirements.
- For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 =
10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example: If CRA1/0 = 10 and ALEW = 1, the V2 = 4 - (1.5 + 0.5) = 2.
V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is deter
mined by the CRA1 and CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 =00,
3 if CRA1/0 =01, 4 if CRA1/0 = 10, and 5 it CRA1/0 = 11).
V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is
determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00,2 if CR1/0= 01,3 if CR1/0= 10,
and 4 if CR1/0 = 11.
V5) This variable represents the programmed length of an entire data read cycle with no ALE. this time is
determined by the DR1 and DR0 bits in the BTRH register. V5 = l if DR1/0 = 00,2 if DR1/0 = 01,3 if DR1/0 =
10, and 4 it DR1/0 = 11.
V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined
by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if
DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11).
V7) This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or
the DRA1, DRA0 in the BTRH register, and the ALEW bit in the BTRL register. Note that during a 16-bit
operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and
second byte bus cycles. V7still applies for the purpose of determining peripheral timing requirements. The
timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no
ALE.
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
45
|
|
Share Link: 