MX10EXA View Datasheet(PDF) - Macronix International

Part Name

Description

Manufacturer

MX10EXA

XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs

Macronix International 

MX10EXA

SnSTATAddress: S0STAT 421 MSB

LSB

S1STAT 425

Bit Addressable

-

-

-

-

FEn BRn OEn STINTn

Reset Value:00H

BIT

SnSTAT.3

SnSTAT.2

SnSTAT.1

SnSTAT.0

SYMBOL

FEn

BRn

OEn

STINTn

FUNCTION

Framing Error flag is set when the receiver fails to see a valid STOP bit at the end

of the frame. Cleared by software.

Break Detect flag is set if a character is received with all bits (including STOP bit)

being logic ‘0’. Thus it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit

9 for Modes 2 and 3. The break detect feature operates independently of the UARTs

and provides the START of Break Detect status bit that a user program may poll.

Cleared by software.

Overrun Error flag is set if a new character is received in the receiver buffer while it

is still full (before the software has read the previous character from the buffer), i.e.,

when bit 8 of a new byte is received while RI in SnCON is still set. Cleared by

software.

This flag must be set to enable any of the above status flags to generate a receive

interrupt (Rln). The only way it can be cleared is by a software write to this register.

Figure 15. Serial Port Extended Status (SnSTAT) Register

(See also Figure 17 regarding Framing Error flag)

INTERRUPT SCHEME

There are separate interrupt vectors for each UART ’ s

transmit and receive functions.

Table 6. Vector Locations for UARTS in XA

Vector Address Interrupt Source Arbitration

A0H - A3H

UART 0 Receiver 7

A4H - A7H

UART 0 Transmitter 8

A8H - ABH

UART I Receiver 9

ACH-AFH

UARTI Transmitter 10

NOTE:

The transmit and receive vectors could contain the same

ISR address to work like a 8051 interrupt scheme

Error Handling, Status Rags and Break Detect

The UARTs in XA has the following error flags; see Fig-

ure 15.

Multiprocessor Communications

Modes 2 and 3 have a special provision for multiproces-

sor communications. in these modes, 9 data bits are

received. The 9th one goes into RB8. Then comes a stop

bit. The port can be programmed such that when the

stop bit is received, the serial port interrupt will be acti-

vated only if RB8 = 1. This feature is enabled by setting

bit SM2 in SCON. A way to use this feature in multipro-

cessor systems is as follows:

When the master processor wants to transmit a block of

data to one of several slaves, it first sends out an ad-

dress byte which identifies the target slave. An address

byte differs from a data byte in that the 9th bit is 1 in an

address byte and 0 in a data byte. With SM2 = 1, no

slave will be interrupted by a data byte. An address byte,

however, will interrupt all slaves, so that each slave can

examine the received byte and see if it is being addressed.

The addressed slave will clear its SM2 bit and prepare to

receive the data bytes that will be coming. The slaves

that weren’t being addressed leave their SM2s set and

go on about their business, ignoring the coming data

bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be

used to check the validity of the stop bit although this is

better done with the Framing Error (FE) flag. In a Mode 1

reception, if SM2 = 1, the receive interrupt will not be

activated unless a valid stop bit is received.

P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

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