MX10EXA View Datasheet(PDF) - Macronix International

Part Name

Description

Manufacturer

MX10EXA

XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs

Macronix International 

MX10EXA

Serial Port Control Register

The serial port control and status register is the Special

Function Register SnCON, shown in Figure 16. This reg-

ister contains not only the mode selection bits, but also

the 9th data bit for transmit and receive (TB8_n and

RB8_n), and the serial port interrupt bits TI_n and RI_n).

TI Flag

In order to allow easy use of the double buffered UART

transmitter feature, the TI_n flag is set by the UART hard-

ware under two conditions. The first condition is the

completion of any byte transmission. This occurs at the

end of the stop bit in modes 1, 2, or 3, or at the end of

the eighth data bit in mode 0. The second condition is

when SnBUF is written while the UART transmitter is

idle. In this case, the TI_n flag is set in order to indicate

that the second UART transmitter buffer is still avail-

able.

Typically, UART transmitters generate one interrupt per

byte transmitted. In the case of the XA UART, one addi-

tional interrupt is generated as defined by the stated con-

ditions for setting the TI_n flag. This additional interrupt

does not occur if double buffering is bypassed as ex-

plained below. Note that if a character oriented approach

is used to transmit data through the UART; there could

be a second interrupt for each character transmitted,

depending on the timing of the writes to SBUF. For this

reason, it is generally better to bypass double buffering

when the UART transmitter is used in character oriented

mode. This is also true if the UART is polled rather than

interrupt driven, and when transmission is character ori-

ented rather than message or string oriented. The inter-

rupt occurs at the end of the last byte transmitted when

the UART becomes idle. Among other things, this allows

a program to determine when a message has been trans-

mitted completely. The interrupt service routine should

handle this additional interrupt.

The recommended method of using the double buffering

in the application program is to have the interrupt ser-

vice routine handle a single byte for each interrupt oc-

currence. In this manner the program essentially does

not require any special considerations for double buffer-

ing. Unless higher priority interrupts cause delays in the

servicing of the UART transmitter interrupt, the double

buffering will result in transmitted bytes being tightly

packed with no intervening gaps.

9-bIt Mode

Please note that the ninth data bit (TB8) is not double

buffered. Care must be taken to insure that the TB8 bit

contains the intended data at the point where it is trans-

mitted. Double buffering of the UART transmitter may be

bypassed as a simple means of synchronizing TB8 to

the rest of the data stream.

Bypassing Double Buffering

The UART transmitter may be used as if it is single buff-

ered. The recommended UART transmitter interrupt ser-

vice routine (ISR) technique to bypass double buffering

first clears the TI_n flag upon entry into the ISR, as in

standard practice. This clears the interrupt that activated

the ISR. Secondly, the TI_n flag is cleared immediately

following each write to SnBUF. This clears the interrupt

flag that would otherwise direct the program to write to

the second transmitter buffer. If there is any possibility

that a higher priority interrupt might become active be-

tween the write to SnBUF and the clearing of the TI_n

flag, the interrupt system may have to be temporarily

disabled during that sequence by clearing, then setting

the EA bit in the IEL register.

P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

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