MX10EXA View Datasheet(PDF) - Macronix International

Part Name

Description

Manufacturer

MX10EXA

XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs

Macronix International 

MX10EXA

SCR Address:440 MSB

Not Bit Addressable

Reset Value:00H

-

-

LSB

-

- PT1 PT0 CM PZ

PT1 PT0

0

0

0

1

1

0

1

1

CM

PZ

OPERATING

Prescaler selection.

Osc/4

Osc/16

Osc/64

Reserved

Compatibility Mode allows the XA to execute most translated 80C51 code on the XA. The

XA register file must copy the 80C51 mapping to data memory and mimic the 80C51

indirect addressing scheme.

Page Zero mode forces all program and data addresses to 16-bits only. This saves stack

space and speeds up execution but limits memory access to 64k.

Figure 5. System Configuration Register (SCR)

TMOD Address:45C

Not Bit Addressable

Reset Value:00H

MSB

GATE C/T M1 M0 GATE C/T

LSB

M1 M0

TIMER 1

TIMER 0

GATE

C/T

Gating control when set. Timer/Counter "n" is enabled only while "INTn" pin is high and "TRn"

control bit is set. When cleared Timer "n" is enabled whenever "TRn" control bit is set.

Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for

Counter operation (input from "Tn" input pin).

M1

M0

OPERATING

0

0

16-bit auto-reload timer/counter

0

1

16-bit non-auto-reload timer/counter

1

0

8-bit auto-reload timer/counter

1

1

Dual 8-bit timer mode (timer 0 only)

Figure 6. Timer/Counter Mode Control (TMOD) Register

P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

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