MTV021 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTV021

Enhanced Super On-Screen Display

Unspecified 

MYSON

TECHNOLOGY

MTV021

Name

PWM4

PWM5

PWM6

PWM7

VDD

VFLB

HTONE /

PWMCK

FBKG

BOUT

GOUT

ROUT

VSS

Pin No.

I/O

N16 N20 N24

Descriptions

O-

- 13 Open-Drain PWM D/A converter 4. The output pulse width is program-

mable by the register of Row 15, Column 27.

O-

- 14 Open-Drain PWM D/A converter 5. The output pulse width is program-

mable by the register of Row 15, Column 28.

O - 11 15 Open-Drain PWM D/A converter 6. The output pulse width is program-

mable by the register of Row 15, Column 29.

O - 12 16 Open-Drain PWM D/A converter 7. The output pulse width is program-

mable by the register of Row 15, Column 30.

- 9 13 17 Digital power supply. Positive 5 V DC supply for internal digital circuitry

and a 0.1uF decoupling capacitor should be connected across to VDD

and VSS.

I 10 14 18 Vertical input. This pin is used to input the vertical synchronizing signal.

It is leading triggered and has an internal pull-up resistor.

O 11 15 19 Half tone output / PWM clock output. This is a multiplexed pin selected

by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B

gain of VGA for the transparent windowing effect.

O 12 16 20 Fast Blanking output. It is used to cut off external R, G, B signals of

VGA while this chip is displaying characters or windows.

O 13 17 21 Blue color output. It is a blue color video signal output.

O 14 18 22 Green color output. It is a green color video signal output.

O 15 19 23 Red color output. It is a red color video signal output.

- 16 20 24 Digital ground. This ground pin is used to internal digital circuitry.

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus

can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

3.1.1 SPI bus

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV021 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

SSB

SCK

SDA

MS

LSB

B

first byte

last byte

FIGURE 1. Data Transmission Protocol (SPI)

3/17

MTV021 Revision 5.0 6/29/1999

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