SEMICONDUCTOR TECHNICAL DATA
64K x 18 Bit Synchronous
Pipelined Cache Tag RAM
The MCM69T618 is a 1M–bit synchronous fast static RAM with integrated tag
compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB
secondary cache as well as to be used as a data RAM for 512KB caches. This
device is organized as 64K words of 18 bits each. It integrates input registers,
output registers, tag comparators, and high speed SRAM onto a single mono-
lithic circuit for reduced parts count in cache tag RAM applications. Synchronous
design allows precise cycle control with the use of an external clock (K). BiCMOS
circuitry reduces the overall power consumption of the integrated functions for
Addresses (SA), data inputs (DQ), write enable (SW), and chip enable (SE0
and SE1) are all controlled through positive–edge–triggered noninverting reg-
isters. Data enable (DE) is sampled on the rising clock edge while output enable
(G) and match output enable (MG) are asynchronous.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
Compare cycles begin as read cycles with output disabled, so compare data
can be loaded into the input register. The comparator compares the read data
with the registered input data, and a match signal is generated. The match output
is also stored by an output register and released to the match output buffer at the
next rising edge of clock (K).
The MCM69T618 operates from a single 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
• MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle
• Single 3.3 V + 10%, – 5% Power Supply
• Pipelined Data Comparator
• Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path
• 64K x 18 Organization Supports Up to 2MB Cache
• Synchronous Data Input Register Load Enable (DE)
• Internally Self–Timed Write Cycle
• Asynchronous Data I/O Output Enable (G)
• Asynchronous Match Output Enable (MG)
• 100–Pin TQFP Package
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