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PDM31532SA15TA View Datasheet(PDF) - Paradigm Technology

Part NamePDM31532SA15TA Paradigm-Technology
Paradigm Technology 
Description64K x 16 CMOS 3.3V Static RAM
PDM31532SA15TA Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Write Cycle 3 Timing Diagram(8) (UB, LB Controlled)
ADDRESSES
tAS
WE
tWC
tAW
tWP
tAH
tCW
CE
tBW
UB, LB
DOUT
DIN
tLZCE(5)
tLZBE(5)
tHZWE(5)
High Impedance
tDS
tDH
Data Stable
PDM31532
AC Electrical Characteristics
Description
-9 (7)
-10 (7)
-12
-15
-20
WRITE Cycle
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Byte pulse width
Address setup time
Address hold from end of write
Write pulse width
Data setup time
Data hold time
Byte disable to output in low Z(1, 5, 8)
Byte enable to output in high Z(1, 5, 8)
Output disable to output in low Z(1, 5, 8)
Output enable to output in high Z(1, 5, 8)
Write disable to output in low Z(1, 5, 8)
Write enable to output in high Z(1, 5, 8)
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC
9 — 10 — 12 — 15 — 20 — ns
tCW
8 — 9 — 10 — 11 — 12 — ns
tAW
8 — 9 — 10 — 11 — 12 — ns
tBW
8 — 9 — 10 — 12 — 13 — ns
tAS
0 — 0 — 0 — 0 — 0 — ns
tAH
0 — 0 — 0 — 0 — 0 — ns
tWP
7 — 7 — 8 — 9 — 10 — ns
tDS
6 — 6 — 7 — 8 — 9 — ns
tDH
0 — 0 — 0 — 0 — 0 — ns
tLZBE 1 — 1 — 1 — 1 — 1 — ns
tHZBE — 7 — 7 — 7 — 8 — 9 ns
tLZOE 0 — 0 — 0 — 0 — 0 — ns
tHZOE — 7 — 7 — 7 — 8 — 9 ns
tLZWE 1 — 1 — 1 — 1 — 1 — ns
tHZWE — 7 — 7 — 7 — 8 — 9 ns
8
Rev. 4.3 - 3/27/98
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