¡ Semiconductor
MSM80C48/49/50, MSM80C35/39/40
AC Characteristics
Parameter
ALE Pulse Width
Address Setup Time (up to ALE)
Address Hold Time (from ALE)
Bus Port Latch Data Setup Time (up to ALE Rising Edge)
Bus Port Latch Data Hold Time (from ALE Rising Edge)
Control Pulse Width (RD, WR)
Control Pulse Width (PSEN)
Data Setup Time (before WR)
Data Hold after Time (after WR)
Data Hold Time (after RD, PSEN)
RD to Data-in
PSEN to Data-in
Address Setup to WR
Address Setup to Data-in
Address Setup to Instruction
Address Float to RD, WR
Address Float to PSEN
Control Pulse Setup Time from ALE (PSEN)
Control Pulse Setup Time from ALE (RD, WR)
Control Pulse up to ALE (RD, WR, PROG)
Control Pulse up to ALE (PSEN)
Port Control Setup Time (up to PROG Falling Edge)
Port Control Hold Time (from PROG Falling Edge)
PROG to Input Data Valid
Input Data Hold Time
Output Data Setup Time
Output Data Hold Time
PROG Pulse Width
Port 2 I/O Setup Time
Port 2 I/O Hold Time
Port Output Data (from ALE)
T0 Cycle
Instruction Execution Time
(VCC=2.5V to 6V (*1), Ta=–40 to +85°C)
VCC=5 V±10% Variable clock
Symbol 11 MHz Clock 0 to 11 MHz
Unit
Min. Max. Min.
Max.
tLL
150 — 3.5t–170
—
ns
tAL
70 — 2t–110
—
ns
tLA
50 —
t–40
—
ns
tBL
110 — 2.5t –115
—
ns
tLB
90 — 1.5 t–45
—
ns
tCC1
480 — 7t–155
—
ns
tCC2
350 — 6t–200
—
ns
tDW
390 — 6t–155
—
ns
tWD
40 — 2t–140
—
ns
tDR
0 110
0
1.5t–30 ns
tRD1
— 350
—
5t–265 ns
tRD2
— 190
—
5t–265 ns
tAW
300 — 6t–245
—
ns
tAD1
— 730
—
12t–360 ns
tAD2
tAFC1
— 460
140 —
—
2t–40
8t–265 ns
—
ns
tAFC2
10 —
10
tLAFC2
60 —
t–30
—
ns
—
ns
tLAFC1 200 —
3t–75
—
ns
tCA1
50 — 1.5t–85
—
ns
tCA2
320 — 4.5t–90
—
ns
tCP
50 — 2t–130
—
ns
tPC
100 — 4t–260
—
ns
tPR
— 650
—
9t–170 ns
tPF
0 140
0
1.5t
ns
tDP
250 — 6t–290
—
ns
tPD
40 — 3t–230
—
ns
tPP
700 — 10t–210
—
ns
tPL
160 — 4.5–250
—
ns
tLP
15 — 1.5t–120
—
ns
tPV
— 510
—
4t+145 ns
tOPRR 270 —
3t
—
ns
tCY
1.36 —
15t
—
ms
Note : Control output : CL=80pF
Bus output : CL=150pF [for 20 pF (tAL, tAFC1, tAFC2)]
*1 Minimum operating voltage is dependent on frequency.
10/20