PRODUCT SPECIFICATION
ML2036
Table 1. Three Level PDN-INH Functions.
PDN-INH
MODE
PDN(1)
PDN-INH
PIN
VI1, Logic “0”
DATA IN
SHIFT REG.
X
Inhibit
PDN(1)
VI2, Inhibit State
Voltage, VSS to
VSS + 0.5V
VI3, Logic “1”
All 0’s
All 0’s
LATI
X
Logic “1”
Logic “1”
SINE WAVE OUTPUT
VOUT = 0V
(10kΩ to AGND)
VOUT goes to approximately VOS at the
next VOS crossing
(See Figure 6)
VOUT = 0V
(10kΩ to AGND)
Note:
1. In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional.
POWER DOWN MODE VOS
0V
INHIBIT MODE
VOS
0V
SCK
SID
LATI
0 1 2 3 4 5 6 7 8 9 10 11 12 131415
VX
|VX| =
VPEAK ,
256
FOR
fOUT
≤
fCLK
2048
|VX| ≤
VPEAK
256
+
VPEAK
SIN
8
π fOUT
fCLK
+
π
512
FOR fOUT >
fCLK
2048
Figure 6. Power Down Mode Waveforms.
REV. 1.0.2 7/26/01
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