ML2036CP View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
ML2036CP
Fairchild Semiconductor
ML2036CP Datasheet PDF : 12 Pages
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ML2036
PRODUCT SPECIFICATION
Pin Configuration
ML2036
14-Pin PDIP (P14)
ML2036
16-Pin Wide SOIC (S16W)
VSS 1
PDN-INH 2
CLK OUT 1 3
14 CLK IN
13 GAIN
12 DGND
CLK OUT 2 4
11 AGND
SCK 5
SID 6
LATI 7
10 VOUT
9 VREF
8 VCC
TOP VIEW
NC
VSS
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
SID
LATI
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TOP VIEW
CLK IN
GAIN
NC
DGND
AGND
VOUT
VREF
VCC
Pin Description (Pin Number in Paranthesis is for SOIC Version)
PIN
1 (2)
2 (3)
3 (4)
4 (5)
5 (6)
6 (7)
7 (8)
8 (9)
9 (10)
10 (11)
11 (12)
12 (13)
13 (15)
14 (16)
NAME
VSS
PDN-INH
CLK
OUT 1
CLK
OUT 2
SCK
SID
LATI
VCC
VREF
VOUT
AGND
DGND
GAIN
CLK IN
FUNCTION
Negative supply (-5V).
Three level input which controls the inhibit and power down modes. Current source pull-up
to VCC.
Digital clock output from the internal clock generator that can drive other devices at fCLK OUT
1 = fCLK IN/2.
Digital clock output from the internal clock generator that can drive other devices at fCLK OUT
2 = fCLK IN/8.
Serial clock. Digital input which clocks in serial data on its rising edges.
Serial input data which programs the frequency of VOUT.
Digital input which latches serial data into the internal data latch on falling edges.
Positive supply (5V).
Reference input. The voltage on this pin determines the peak-to-peak swing of VOUT. VREF
can be tied to VCC.
Analog output.
Analog ground. All analog inputs and outputs are referenced to this point.
Digital ground. All digital inputs and outputs are referenced to this point.
Sets VOUT peak amplitude to VREF or VREF/2. Current source pull-down to DGND.
Clock input. The internal clock can be generated by tying a 3 to 12MHz crystal from this pin
to DGND, or by applying a digital clock signal directly to the pin.
2
REV. 1.0.2 7/26/01
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