ML2035C View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
ML2035C Datasheet PDF : 9 Pages
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ML2035
SCK
SID
LATI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 4. Serial Interface Timing.
FUNCTIONAL DESCRIPTION (Continued)
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the
falling edge of LATI. To insure that true data is loaded into
the data latch from the shift register, LATI falling edge
should occur when SCK is low, as shown in figure 1. LATI
should be low while shifting data into the shift register to
avoid inadvertently entering the power down mode. Note
that all data is entered and latched on the edges, not
levels, of SCK and LATI.
POWER DOWN MODE
The power down mode of the ML2035 can be selected by
entering all zeros in the shift register and applying a logic
“1” to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
and VOUT goes to 0V as shown in Figure 5 and appears as
10kΩ to ground. The master clock, CLK IN, can be left
active or removed during power down mode.
POWER SUPPLIES
The analog circuits in ML2035 are powered from VCC to
VSS and are referenced to GND. The digital circuits in the
device are powered from VCC to GND.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors
from VCC to GND and VSS to GND as physically close to
the device as possible.
POWER DOWN MODE
VOS
0V
SCK
SID
LATI
0 1 2 3 4 5 6 7 8 9 10 11 12 131415
Figure 5. Power Down Mode Waveforms.
REV. 1.0 10/10/2000
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