AD7248ATQ3 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7248ATQ3 Datasheet PDF : 16 Pages
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AD7245A/AD7248A–SPECIFICATIONS (VDD = +12 V to +15 V,1VSS = O V or –12 V to –15 V,1
AGND = DGND = O V, RL = 2 k⍀, CL = 1OO pF. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A2
B2
T2
Version Version Version Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
Relative Accuracy @ +25°C3
± 3/4
TMIN to TMAX
±1
TMIN to TMAX
Differential Nonlinearity3
±1
Unipolar Offset Error @ +25°C3
±3
TMIN to TMAX
±5
Bipolar Zero Error @ +25°C3
±3
TMIN to TMAX
±5
DAC Gain Error3, 6
±2
Full-Scale Output Voltage Error7 @ +25°C ± 0.2
∆Full Scale/∆VDD
∆Full Scale/∆VSS
Full-Scale Temperature Coefficient8
± 0.06
± 0.01
± 30
12
± 1/2
± 3/4
± 1/2
±1
±3
±5
±2
±4
±2
± 0.2
± 0.06
± 0.01
± 30
REFERENCE OUTPUT
REF OUT @ +25°C
∆REF OUT/∆VDD
Reference Temperature Coefficient
Reference Load Change
(∆REF OUT vs. ∆I)
4.99/5.01 4.99/5.01
2
2
± 25
± 25
–1
–1
12
± 1/2
± 3/4
±1
±3
±5
±2
±4
±2
± 0.2
± 0.06
± 0.01
± 40
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
ppm of FSR/°C max
VDD = 15 V ± 5%
Guaranteed Monotonic
VSS = 0 V or –12 V to –15 V4
Typical Tempco is ± 3 ppm of FSR5/°C.
ROFS connected to REF OUT; VSS = –12 V to –15 V4
Typical Tempco is ± 3 ppm of FSR5/°C.
VDD = +15 V
VDD = +12 V to +15 V4
VSS = –12 V to –15 V4
VDD = +15 V
4.99/5.01 V min/V max
2
mV/V max
± 35
ppm/°C typ
–1
mV max
VDD = +15 V
VDD = +12 V to +15 V4
Referenee Load Current Change (0–100 µA)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance9
2.4
2.4
0.8
0.8
± 10
± 10
8
8
2.4
V min
0.8
V max
± 10
µA max
8
pF max
VIN = 0 V to VDD
ANALOG OUTPUTS
Output Range Resistors
Output Voltage Ranges10
Output Voltage Ranges10
DC Output Impedance
AC CHARACTERISTICS9
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Output Voltage Slew Rate
Digital Feedthrough3
Digital-to-Analog Glitch Impulse
15/30 15/30
+5, +10 +5, +10
+5, +10, +5, +10,
±5
±5
0.5
0.5
15/30 kΩ min/kΩ max
+5, +10 V
+5, +10,
±5
V
0.5
Ω typ
7
7
7
7
2
2
10
10
30
30
10
µs max
10
µs max
1.5
V/µs min
10
nV-s typ
30
nV-s typ
VSS = 0 V; Pin Strappable
VSS = –12 V to –15 V;4 Pin Strappable
Settling Time to Within ± 1/2 LSB of Final Value
DAC Latch All 0s to All 1s
DAC Latch All 1s to All 0s; VSS = –12 V to –15 V4
POWER REQUIREMENTS
VDD
VSS
IDD @ +25°C
TMlN to TMAX
ISS (Dual Supplies)
+10.8/
+16.5
–10.8/
–16.5
9
10
3
+11.4/
+15.75
–11.4/
–15.75
9
10
3
+11.4/
+15.75
–11.4/
–15.75
9
12
5
V min/
V max
V min/
V max
mA max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 5 mA
Output Unloaded
Output Unloaded; Typically 2 mA
NOTES
1Power supply tolerance is ± 10% for A Version and ± 5% for B and T Versions.
2Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C.
3See Terminology.
4With appropriate power supply tolerances.
5FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and ± 5 V output ranges.
6This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7This error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and ± 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the
0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.
8Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = +25°C to TMIN or TMAX.
9Sample tested at +25°C to ensure compliance.
100 V to +10 V output range is available only when VDD ≥ +14.25 V.
Specifications subject to change without notice.
–2–
REV. A
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