PROGRAMMER’S GUIDE (continued)
NOTE: I SMPL may be set high, even if F SMPL is already
set high. I SMPL is not automatically cleared low.
The length of time required to acquire the data is depen-
dent on the crystal frequency (tied to pins 1 and 24) or OSCin
frequency. The formula is: T = 3584/f; where T is the ac-
quisition time in seconds and f is the frequency at OSCin in
hertz. After the I SMPL bit is set, the EOC bit is set high after
the acquisition time T above, and data is available to be read.
Step 3: Read the Serial Data
To read the ADC value, set the Read A bit in the C Register
to a 1. I SMPL must not be changed; it must be a 1.
Take the ENB pin low and shift out 8 bits. The value is con-
tained in the least–significant 6 bits. In addition, the EOC bit
should be checked to ensure it is a 1; this indicates that the
conversion was complete before the data was read. If EOC is
a 0, the conversion result is not valid.
The In C bit is valid and indicates the logic level present on
the Input C pin. (Alternatively, 9 or 16 bits could be shifted out
if the user desires to read both the In C and In D bits.)
NOTE: When the Read A bit is set to a 1, writing to any
register is inhibited. After the serial shift which reads the A
Register occurs, Read A is automatically cleared to a 0.
CAUTION
If both Read A and Read F are set simultaneously,
a Read A Register operation is performed and the
Read F Register request is ignored.
READING THE F REGISTER
The F Register contains the binary representation of the
Frequency Counter’s value plus the Count Complete flag
(CC). The CC bit must be a 1 to indicate a valid count. Also,
the F Register has a bit which indicates the logic level on the
Input D pin.
Reading the Logic Level on the Input D Pin
Step 1: Store the Value in the Shift Register
To store the value, set the Read F bit in the C Register to a
1. The digital value present at the Input D pin during the fal-
ling edge of ENB on the read cycle is stored in the shift regis-
ter.
Step 2: Read the Serial Data
To read the Input D value, take the ENB pin low and shift
out 24 bits. The Input D value is contained in the In D bit.
NOTE: In D may also be read from the A Register.
Reading the Frequency Counter Value
Step 1: Initialize
To initialize the counter, clear the F SMPL bit in the R Reg-
ister to a 0. At this time, the Read F bit in the C Register must
be 0. The HF/VHF bit in the R Register must be a 0 for HF–
MF operation or 1 for VHF operation. The ACQ (Acquisition
Window) bit must be a 0 for a narrow acquisition window or a
1 for a wide window. The formula for the window:
+ ) t
2(19 2a)
f
where t = acquisition window (in seconds), a = logic level of
acquisition bit (0 or 1), f = crystal frequency or OSCin
frequency in hertz.
Step 2: Acquire the Count
To sample the frequency, set the F SMPL bit in the R Reg-
ister to a 1. The Read F bit must not be changed; it must be
a 0.
CAUTION
F SMPL must not be set if I SMPL is already set
high.
The data is available to be read after the acquisition win-
dow time above. The CC bit is set high immediately after the
acquisition is complete.
Step 3: Read the Serial Data
To read the F Counter value, set the Read F bit in the C
Register to a 1. F SMPL must not be changed; it must be a 1.
Take the ENB pin low and shift out 24 bits. The value is con-
tained in the least–significant 22 bits. In addition, the CC bit
should be checked to ensure it is a 1; this indicates that the
count was complete before the data was read. If CC is a 0,
the count is not valid. The In D bit is valid and indicates the
logic level present on the Input D pin.
NOTE: When the Read F bit is set to a 1, writing to any
register is inhibited. After the serial shift which reads the F
Register occurs, Read F is automatically cleared to a 0.
CAUTION
If both Read A and Read F are set simultaneously,
a Read A Register operation is performed and the
Read F Register request is ignored.
MOTOROLA
MC145173
27