MC13180 View Datasheet(PDF) - Motorola => Freescale
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MC13180 Datasheet PDF : 58 Pages
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Functional Description
4 Functional Description
Note: In the following description, control bits contained in the MC13180 register map for various
functions will be identified by register number and bit number(s). For example, bit R4/8 references bit 8 of
register 4 while R5/9-3 identifies bits 9 through 3, inclusive, of register 5 (decimal notation). Unless
otherwise noted, a default register map configuration as listed in Figure 4 is assumed.
4.1 Overview
The MC13180 is a complete RF transceiver for Bluetooth applications. The device, when coupled with an
MC71000 controller or any controller containing an integrated Joint Detection/Minimum Length Sequence
Estimator (JD/MLSE) digital decoder, exhibits superior RF performance with small size and low cost.
Only minimal external components are required to complete the RF link of a Bluetooth system.
4.2 MC13180 States
Figure 11 illustrates the various states which the MC13180 can assume. A description of each state
follows.
4.3 OFF State
In the OFF state, no power is being applied to the VCCRF or VDDINT of the device. During this state, all
digital inputs should be held at ground to avoid forward biasing internal ESD diodes.
4.4 POWER UP State
During this state, power is applied to the device in an orderly fashion. All digital inputs should continue to
be held at ground.
Since VDDINT of the device must always be less than or equal to the VCCRF supplied to the device, it is
generally desired to first allow the VCCRF to rise and stabilize, then follow with applying the VDDINT
supply. This prevents internal protection diodes from forward biasing.
SPI operations are not allowed during this state.
4.5 RESET State
The RESET state can be entered at any time from any state with the exception of the OFF and POWER UP
states. During the RESET state, SPI operations are forbidden.
The RESET state places the entire contents of the internal register map into a known condition. All digital
outputs are active and driven to a logic low. The SDATA I/O pin is configured as an input, and the
RFDATA I/O pin is configured as an output. The crystal oscillator is inactive and therefore the CLK
output remains at a static low level.
4.6 CONFIG State
Once the RES pin is de-asserted, the crystal oscillator and data clock PLL of the device become active. The
CLK output will attempt to synthesize a clock frequency based upon the crystal oscillator frequency and
values loaded into the data clock N and R registers. These values assume an initial reference frequency of
13 MHz and the data clock values are initialized from reset to synthesize 24 MHz from this reference.
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