MBM29LV650UE/651UE-90/12
2. AC Characteristics
• Read Only Operations Characteristics
Parameter
Symbols
JEDEC Standard
Description
Test Setup
90
(Note)
tAVAV
tRC Read Cycle Time
— Min. 90
tAVQV
tACC Address to Output Delay
CE = VIL
OE = VIL
Max.
90
tELQV
tCE Chip Enable to Output Delay
OE = VIL Max. 90
tGLQV
tOE Output Enable to Output Delay
— Max. 35
tEHQZ
tDF Chip Enable to Output HIGH-Z
— Max. 30
tGHQZ
tDF Output Enable to Output HIGH-Z
— Max. 30
tAXQX
tOH
Output Hold Time From Address,
CE or OE, Whichever Occurs First
— Min.
0
—
tREADY RESET Pin Low to Read Mode
— Max. 20
12
(Note)
Unit
120 ns
120 ns
120 ns
50 ns
30 ns
30 ns
0
ns
20 µs
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29LV650UE/651UE-90)
1 TTL gate and 100 pF (MBM29LV650UE/651UE-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
Device
Under
Test
CL
3.3 V
IN3064
or Equivalent
2.7 kΩ
6.2 kΩ
Diodes = IN3064
or Equivalent
Figure 4 Test Conditions
31