MAX9310A View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX9310A

1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs

Maxim Integrated 

1:5 Clock Driver with Selectable LVPECL

Inputs/Single-Ended Inputs and LVDS Outputs

AC ELECTRICAL CHARACTERISTICS

(VCC - GND = 3V to 3.6V, outputs terminated with 100Ω ±1%, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%),

VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V,

unless otherwise noted.) (Notes 1 and 6)

PARAMETER SYMBOL CONDITIONS

-40°C

+25°C

+85°C

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

Propagation

Delay CLK_,

CLK_ to Q_, Q_

tPHL,

tPLH

Figure 2

250 340 600 250 340 600 250 340 600 ps

Output-to-

Output Skew

Part-to-Part

Skew

Added Random

Jitter

tSKOO (Note 7)

tSKPP (Note 8)

fIN = 1.0GHz,

tRJ clock pattern

(Note 9)

10

30

145

0.3 1.0

8

25

145

0.3 1.0

20

45

ps

145 ps

0.3

1.0

ps

(RMS)

Added

Deterministic

Jitter

fIN = 1.0Gsps,

tDJ

223 - 1 PRBS

pattern (Note 9)

50

60

50

60

50

60

ps

(P-P)

Operating

Frequency

fMAX VOD ≥ 250mV

1.0

1.0

1.0

GHz

Differential

Output Rise/Fall

Time

tR/tF

20% to 80%,

Figure 2

140 205 300 140 205 300 140 205 300 ps

Note 1: Measurements are made with the device in thermal equilibrium.

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and

characterized over the full operating temperature range.

Note 4: Use VBB only for inputs that are on the same device as the VBB reference.

Note 5: All pins are open except VCC and GND, all outputs are loaded with 100Ω differentially.

Note 6: Guaranteed by design and characterization. Limits are set to ±6 sigma.

Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge

transition.

Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions

for a same-edge transition.

Note 9: Device jitter added to the input signal.

4 _______________________________________________________________________________________

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