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MAX6723AUTYDD4-T View Datasheet(PDF) - Maxim Integrated

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MAX6723AUTYDD4-T Datasheet PDF : 18 Pages
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Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Detailed Description
Supply Voltages
The MAX6715A–MAX6729A/MAX6797A µP supervisory
circuits maintain system integrity by alerting the µP to
fault conditions. These ICs are optimized for systems
that monitor two or three supply voltages. The output-
reset state is guaranteed to remain valid while either
VCC1 or VCC2 is above 0.8V.
Threshold Levels
Input-voltage threshold level combinations are indicat-
ed by a two-letter code in the Reset Voltage Threshold
Suffix Guide (Table 1). Contact factory for availability of
other voltage threshold combinations.
Reset Outputs
The MAX6715A–MAX6729A/MAX6797A provide an
active-low reset output (RST) and the MAX6725A/
MAX6726A also provide an active-high (RST) output.
RST, RST, RST1, and RST2 are asserted when the volt-
age at either VCC1 or VCC2 falls below the voltage
threshold level, RSTIN drops below threshold, or MR is
pulled low. Once reset is asserted, it stays low for the
reset timeout period (see Table 2). If VCC1, VCC2, or
RSTIN goes below the reset threshold before the reset
timeout period is completed, the internal timer restarts.
The MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A contain
open-drain reset outputs, while the MAX6716A/
MAX6726A/MAX6729A/MAX6797A contain push-pull
reset outputs. The MAX6727A provides two separate
open-drain RST outputs driven by the same internal logic.
Manual-Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts the reset output. Reset remains asserted while
MR is low for the reset timeout period (tRP) after MR
returns high. This input has an internal 50kpullup
resistor to VCC1 and can be left unconnected if not
used. MR can be driven with CMOS logic levels, or with
open-drain/collector outputs. Connect a normally open
momentary switch from MR to GND to create a manual-
reset function; external debounce circuitry is not
required. If MR is driven from long cables or if the
device is used in a noisy environment, connect a 0.1µF
capacitor from MR to GND to provide additional noise
Adjustable Input Voltage
The MAX6719A/MAX6720A and MAX6723A–MAX6727A
provide an additional input to monitor a third system volt-
age. The threshold voltage at RSTIN is typically 626mV.
Connect a resistor-divider network to the circuit as shown
in Figure 1 to establish an externally controlled threshold
voltage, VEXT_TH.
VEXT_TH = 626mV((R1 + R2)/R2)
Low-leakage current at RSTIN allows the use of large-
valued resistors resulting in reduced power consump-
tion of the system.
Watchdog Input
The watchdog monitors µP activity through the watch-
dog input (WDI). To use the watchdog function, con-
nect WDI to a bus line or µP I/O line. When WDI
remains high or low for longer than the watchdog time-
out period, the reset output asserts.
The MAX6721A–MAX6729A/MAX6797A include a dual-
mode watchdog timer to monitor µP activity. The flexi-
ble timeout architecture provides a long period initial
watchdog mode, allowing complicated systems to
complete lengthy boots, and a short period normal
watchdog mode, allowing the supervisor to provide
quick alerts when processor activity fails. After each
reset event (VCC power-up/brownout, manual reset, or
watchdog reset), there is a long initial watchdog period
of 35s minimum. The long watchdog period mode pro-
vides an extended time for the system to power-up and
fully initialize all µP and system components before
assuming responsibility for routine watchdog updates.
Figure 1. Monitoring a Third Voltage
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