|Description||18-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO|
|MAX11209 Datasheet PDF : 27 Pages |
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
GPIO1 General-Purpose I/O 1. Register controllable using SPI.
GPIO2 General-Purpose I/O 2. Register controllable using SPI.
GPIO3 General-Purpose I/O 3. Register controllable using SPI.
GND Ground. Ground reference for analog and digital circuitry.
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage
between AVDD and GND.
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a volt-
age between AVDD and GND.
AINN Negative Fully Differential Analog Input
AINP Positive Fully Differential Analog Input
AVDD Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND.
DVDD Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to GND.
Active-Low, Chip-Select Logic Input
Serial-Data Input. Data present at DIN is shifted to the device’s internal registers at the rising edge of the
serial clock at SCLK, when the device is accessed for an internal register write or for a command opera-
Data Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data
RDY/DOUT output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the falling edge of SCLK.
SCLK Serial-Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. When external clock mode is selected (EXTCLK = 1), provide a 2.4576MHz
CLK or 2.048MHz clock signal at CLK. Other frequencies can be used, but the data rate and digital filter
notch frequencies scale accordingly.
GPIO4 General-Purpose I/O 4. Register controllable using SPI.
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