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MAX11209 View Datasheet(PDF) - Maxim Integrated

Part NameMAX11209 MaximIC
Maxim Integrated MaximIC
Description18-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
MAX11209 Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MAX11209/MAX11211
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Pin Configuration
TOP VIEW
+
GPIO1 1
GPIO2 2
GPIO3 3
GND 4
MAX11209
MAX11211
REFP 5
REFN 6
AINN 7
AINP 8
QSOP
16 GPIO4
15 CLK
14 SCLK
13 RDY/DOUT
12 DIN
11 CS
10 DVDD
9 AVDD
Pin Description
PIN
NAME
FUNCTION
1
GPIO1 General-Purpose I/O 1. Register controllable using SPI.
2
GPIO2 General-Purpose I/O 2. Register controllable using SPI.
3
GPIO3 General-Purpose I/O 3. Register controllable using SPI.
4
GND Ground. Ground reference for analog and digital circuitry.
5
REFP
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage
between AVDD and GND.
6
REFN
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a volt-
age between AVDD and GND.
7
AINN Negative Fully Differential Analog Input
8
AINP Positive Fully Differential Analog Input
9
AVDD Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND.
10
DVDD Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to GND.
11
CS
Active-Low, Chip-Select Logic Input
Serial-Data Input. Data present at DIN is shifted to the device’s internal registers at the rising edge of the
12
DIN
serial clock at SCLK, when the device is accessed for an internal register write or for a command opera-
tion.
Data Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data
13
RDY/DOUT output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the falling edge of SCLK.
14
SCLK Serial-Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. When external clock mode is selected (EXTCLK = 1), provide a 2.4576MHz
15
CLK or 2.048MHz clock signal at CLK. Other frequencies can be used, but the data rate and digital filter
notch frequencies scale accordingly.
16
GPIO4 General-Purpose I/O 4. Register controllable using SPI.
8  
Maxim Integrated
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