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MAX11209 View Datasheet(PDF) - Maxim Integrated

Part NameMAX11209 MaximIC
Maxim Integrated MaximIC
Description18-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
MAX11209 Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MAX11209/MAX11211
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Absolute Input Voltage
Low input voltage
Buffers disabled
Buffers enabled
High input voltage
Buffers disabled
Buffers enabled
VGND -
30mV
VGND +
100mV
V
VAVDD +
30mV
VAVDD -
100mV
DC Input Leakage
AIN Dynamic Input Current
REF Dynamic Input Current
AIN Input Capacitance
REF Input Capacitance
AIN Voltage Range
Input Sampling Rate
REF Voltage Range
Sleep mode
Buffer disabled
Buffer enabled
Buffer disabled
Buffer enabled
Buffer disabled
Buffer disabled
Unipolar
Bipolar
LINEF = 0
fS
LINEF = 1
Buffers disabled
Buffers enabled
0
-VREF
0
0.1
Q1
Q1.4
Q20
Q2.1
Q30
5
7.5
246
204.8
VREF
+VREF
VAVDD
VAVDD
- 0.1
FA
FA/V
nA
FA/V
nA
pF
pF
V
kHz
V
REF Sampling Rate
LINEF = 0
LINEF = 1
LOGIC INPUTS (SCLK, CLK, DIN, GPIO1–GPIO4)
Input Current
Input leakage current
246
kHz
204.8
Q1
FA
Input Low Voltage
VIL
0.3 x
VDVDD
V
Input High Voltage
VIH
Input Hysteresis
VHYS
60Hz line frequency
External Clock
55Hz line frequency
50Hz line frequency
LOGIC OUTPUTS (RDY/DOUT, GPIO1–GPIO4)
Output Low Level
VOL IOL = 1mA; also tested for VDVDD = 3.6V
Output High Level
VOH IOH = 1mA; also tested for VDVDD = 3.6V
Leakage Current
Output Capacitance
High-impedance state
High-impedance state
0.7 x
VDVDD
200
2.4576
2.25275
2.048
0.4
0.9 x
VDVDD
Q500
9
V
mV
MHz
V
V
nA
pF
Maxim Integrated
  3
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