MAX11209EEE View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX11209EEE

18-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO

Maxim Integrated 

MAX11209/MAX11211

18-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

CTRL2: Control 2 Register

The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the

direction and values of the digital I/O ports.

Table 13. CTRL2 Register (Read/Write)

BIT

BIT NAME

DEFAULT

B7

DIR4

0

B6

DIR3

0

B5

DIR2

0

B4

DIR1

0

B3

DIO4

1

B2

DIO3

1

B1

DIO2

1

B0

DIO1

1

DIR[4:1]: The direction bits configure the direction of the DIO bit. When a DIR bit is set to 0, the associated DIO bit

is configured as an input and the value returned by a read of the DIO bit is the value being driven on the associated

GPIO. When a DIR bit is set to 1, the associated DIO bit is configured as an output and the GPIO port is driven to a

logic value of the associated DIO bit.

DIO[4:1]: The data input/output bits are bits associated with the GPIO ports. When a DIO is configured as an input,

the value read from the DIO bit is the logic value being driven at the GPIO port. When the direction is configured as an

output, the GPIO port is driven to a logic value associated with the DIO bit.

CTRL3: Control 3 Register

The byte-wide CTRL3 register is a bidirectional read/write register. The CTRL3 register controls the operation and

calibration of the device.

Table 14. CTRL3 Register (Read/Write)

BIT

BIT NAME

DEFAULT

B7

DGAIN2*

0

B6

DGAIN1*

0

B5

DGAIN0*

0

*These DGAIN_ bits are don’t-care bits for the MAX11209.

B4

NOSYSG

1

B3

NOSYSO

1

B2

NOSCG

1

B1

NOSCO

1

B0

RESERVED

0

DGAIN[2:0] (MAX11209 only): The digital gain bits control the input referred gain. With a gain of 1, the input range is

0 to VREF (unipolar) or ±VREF (bipolar). As the gain in increased by 2x, the input range is reduced to 0 to VREF/gain

or ±VREF/gain. Digital gain is applied to the final offset and gain-calibrated digital data. The DGAIN[2:0] bits decode

to digital gains as follows:

000 = 1

100 = 16

001 = 2

101 = 32

010 = 4

110 = 64

011 = 8

111 = 128

NOSYSG: The no-system gain bit, NOSYSG, controls the system gain calibration coefficient. A 1 in this bit location disables

the use of the system gain value when computing the final offset and gain corrected data value. A 0 in this location enables

the use of the system gain value when computing the final offset and gain corrected data value.

NOSYSO: The no system offset bit, NOSYSO, controls the system offset calibration coefficient. A 1 in this location disables

the use of the system offset value when computing the final offset and gain corrected data value. A 0 in this location enables

the use of the system offset value when computing the final offset and gain corrected data value.

NOSCG: The no self-calibration gain bit, NOSCG, controls the self-calibration gain calibration coefficient. A 1 in this location

disables the use of the self-calibration gain value when computing the final offset and gain corrected data value. A 0 in this

location enables the use of the self-calibration gain value when computing the final offset and gain corrected data value.

NOSCO: The no self-calibration offset bit, NOSCO, controls the use of the self-calibration offset calibration coefficient. A 1 in

this location disables the use of the self-calibration offset value when computing the final offset and gain corrected data value.

A 0 in this location enables the use of the self-calibration offset value when computing the final offset and gain corrected data

value.

20  

Maxim Integrated

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