18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
CTRL1: Control 1 Register
The byte-wide CTRL1 register is a bidirectional read/write register. The byte written to the CTRL1 register indicates if
the part converts continuously or single cycle, if an external or internal clock is used, if the reference and signal buffers
are activated, the format of the data when in bipolar mode, and if the analog signal input range is unipolar or bipolar.
Table 12. CTRL1 Register (Read/Write)
LINEF: Use the line frequency bit, LINEF, to select if the data rate is centered for 50Hz power mains or 60Hz power
mains. To select data rates for 50Hz power mains, write 1 to LINEF and to select data rates for 60Hz power mains,
write 0 to LINEF.
U/B: The unipolar/bipolar bit, U/B, selects if the input range is unipolar or bipolar. A 1 in this bit location selects a uni-
polar input range and a 0 selects a bipolar input range.
EXTCLK: The external clock bit, EXTCLK, controls the selection of the system clock. A 1 enables an external clock as
system clock, whereas as a 0 enables the internal clock.
REFBUF: The reference buffer bit, REFBUF, enables/disables the reference buffers. A 1 enables the reference buffers.
A 0 powers down the reference buffers and the reference inputs bypass the reference buffers when driving the ADC.
SIGBUF: The signal buffer, SIGBUF, enables/disables the signal buffers. A 1 enables the signal buffer. A 0 powers
down the signal buffers and the analog signal inputs bypass the signal buffers when driving the ADC.
FORMAT: The format bit, FORMAT, controls the digital format of the data. Unipolar data is always in offset binary for-
mat. The bipolar format is two’s complement if the FORMAT bit is set to 0 or offset binary if the FORMAT bit is set to 1.
SCYCLE: The single-cycle bit, SCYCLE, determines if the device runs in “no-latency” single-conversion mode
(SCYCLE = 1) or if the device runs in “latent” continuous-conversion mode (SCYCLE = 0). When in single-cycle conver-
sion mode, the device completes one no-latency conversion and then powers down into a leakage-only state. When
in continuous-conversion mode, the part is continuously converting and the first three data from the part are incorrect
due to the SINC4 filter latency.
Important Note: When operating in continuous-conversion mode (SCYCLE = 0), it is recommended to keep CS low to
properly detect the end of conversion. The end of conversion is signaled by RDY/DOUT changing from 0 to 1. The tran-
sition of RDY/DOUT from 0 to 1 must be used to synchronize the DATA register read back. If the RDY/DOUT output is
not used to synchronize the DATA read back, a timing hazard exists where the DATA register is updated internally after
a conversion has completed simultaneously with the DATA register being read out, causing an incorrect read of DATA.