MITSUBISHI LSIs
M6MGB/T162S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Write cycle (S-CE control mode)
S-A-1~A17
S-CE
WE#
DQ0~7
tsu (A)
(Note4)
(Note3)
tCW
tsu (CE)
trec (W)
tsu (D) th (D)
DATA IN
STABLE
(Note3)
Note 3: Hatching indicates the state is "don't care".
Note 4: When the falling edge of WE# is simultaneously or priorto the rising edge of S-CE,
the outputs are maintained in the high impedance state.
Note 5: Don't apply inverted phase signal externally when DQ pin is in output mode.
28
Sep. 1999 , Rev.2.0