M16C62A View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M16C62A

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsumi 

Udenvdeelropment

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Mitsubishi microcomputers

M16C / 62P Group

Bus

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(9) External Bus Status When Internal Area Accessed

Table 1.7.6 shows the external bus status when the internal area is accessed.

Table 1.7.6. External Bus Status When Internal Area Accessed

Item

SFR accessed

Internal ROM, RAM accessed

A0 to A19

Address output

Maintain status before accessed

address of external area or SFR

D0 to D15

When read

When write

High-impedance

Output data

High-impedance

Undefined

RD, WR, WRL, WRH

RD, WR, WRL, WRH output

Output “H”

BHE

BHE output

Maintain status before accessed

status of external area or SFR

CS0 to CS3

Output “H”

Output “H”

ALE

Output “L”

Output “L”

(10) Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits

in the CSR register, and the CSE register.

________

To use the RDY signal, set the corresponding CS3W to CS0W bit to “0”. Figure 1.7.6 shows the CSE

register. Table 1.7.7 shows the software wait related bits and bus cycles. Figure 1.7.7 and 1.7.8 show the

typical bus timings using software wait.

Chip select expansion control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

CSE

Address

001B16

After reset

0016

Bit symbol

Bit name

Function

RW

CSE00W

CS0 wait expansion bit b1 b0

(Note) 0 0: 1 wait

RW

0 1: 2 waits

CSE01W

1 0: 3 waits

1 1: Must not be set

RW

CSE10W

CS1 wait expansion bit b3 b2

(Note) 0 0: 1 wait

RW

0 1: 2 waits

CSE11W

1 0: 3 waits

1 1: Must not be set

RW

CSE20W

CS2 wait expansion bit

(Note)

b5 b4

0 0: 1 wait

0 1: 2 waits

RW

CSE21W

1 0: 3 waits

1 1: Must not be set

RW

CSE30W

CS3 wait expansion bit b7 b6

(Note)

0 0: 1 wait

0 1: 2 waits

RW

CSE31W

1 0: 3 waits

RW

1 1: Must not be set

Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to

CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “

002” before setting it.

Figure 1.7.6. CSE Register

40

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