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M48Z58-70MH1 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z58-70MH1
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z58-70MH1 Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Operating modes
2
Operating modes
M48Z58, M48Z58Y
Note:
2.1
The M48Z58/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below battery
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
Table 2. Operating modes
Mode
VCC
E
G
W DQ0-DQ7
Deselect
WRITE
READ
4.75 to 5.5V
or
4.5 to 5.5V
VIH
X
X
VIL
X
VIL
VIL
VIL
VIH
READ
VIL
VIH
VIH
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
DIN
DOUT
High Z
High Z
Deselect
≤ VSO(1)(1)
X
X
X
High Z
1. See Table 10 on page 16 for details.
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Power
Standby
Active
Active
Active
CMOS standby
Battery back-up
mode
Read mode
The M48Z58/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. Thus, the unique address specified by the 13 Address Inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within
Address Access time (tAVQV) after the last address input signal is stable, providing that the E
and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable
Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
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