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M48Z512A-70CS9 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z512A-70CS9
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z512A-70CS9 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48Z512A, M48Z512AY
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A/M48Z512AY
Symbol
Parameter
-70
-85
Min
Max
Min
Max
tAVAV
Write Cycle Time
70
85
tAVWL
Address Valid to Write Enable Low
0
0
tAVEL
Address Valid to Chip Enable Low
0
0
tWLWH
Write Enable Pulse Width
55
65
tELEH
Chip Enable Low to Chip Enable High
55
75
tWHAX
Write Enable High to Address Transition
5
5
tEHAX
Chip Enable High to Address Transition
15
15
tDVWH
Input Valid to Write Enable High
30
35
tDVEH
Input Valid to Chip Enable High
30
35
tWHDX
Write Enable High to Input Transition
0
0
tEHDX
Chip Enable High to Input Transition
10
10
tWLQZ (1, 2) Write Enable Low to Output Hi-Z
25
30
tAVWH
Address Valid to Write Enable High
65
75
tAVEH
Address Valid to Chip Enable High
65
75
tWHQX (1, 2) Write Enable High to Output Transition
5
5
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE MODE
The M48Z512A/512AY is in the Write Mode when-
ever W and E are active. The start of a write is ref-
erenced from the latter occurring falling edge of W
or E. A write is terminated by the earlier rising edge
of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of tE-
HAX from E or tWHAX from W prior to the initiation
of another read or write cycle. Data-in must be val-
id tDVEH or tDVWH prior to the end of write and re-
main valid for tEHDX or tWHDX afterward. G should
be kept high during write cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
9/17
 

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