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M48Z129Y View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z129Y Datasheet PDF : 16 Pages
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M48Z129Y*, M48Z129V
Table 3. READ Mode AC Characteristics
M48Z129Y
M48Z129V
Symbol
Parameter(1)
–70
–85
Min
Max
Min
Max
tAVAV
READ Cycle Time
70
85
tAVQV
Address Valid to Output Valid
70
85
tELQV
Chip Enable Low to Output Valid
70
85
tGLQV
Output Enable Low to Output Valid
35
45
tELQX(2)
Chip Enable Low to Output Transition
5
5
tGLQX(2) Output Enable Low to Output Transition
3
5
tEHQZ(2) Chip Enable High to Output Hi-Z
30
40
tGHQZ(2) Output Enable High to Output Hi-Z
20
25
tAXQX
Address Transition to Output Transition
5
5
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 10., page 11).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE Mode
The M48Z129Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are ac-
tive. The start of a WRITE is referenced from the
latter occurring falling edge of W or E. A WRITE is
terminated by the earlier rising edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of
tEHAX from Chip Enable or tWHAX from WRITE En-
able prior to the initiation of another READ or
WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX after-
ward. G should be kept high during WRITE cycles
to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on
W will disable the outputs tWLQZ after W falls.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveform
A0-A16
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI02382
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