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M48Z129Y-85PM1TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z129Y-85PM1TR
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z129Y-85PM1TR Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48Z129Y*, M48Z129V
READ Mode
The M48Z129Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 ad-
dress inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
Figure 5. Address Controlled, READ Mode AC Waveforms
A0-A16
tAVAV
VALID
tAXQX
tAVQV
DQ0-DQ7
DATA VALID
DATA VALID
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
AI02324
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
A0-A16
E
G
DQ0-DQ7
tAVQV
tELQV
tAVAV
VALID
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
AI01197
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