M48T86MH View Datasheet(PDF) - STMicroelectronics
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Description
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M48T86MH Datasheet PDF : 23 Pages
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M48T86
Table 9. AC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Symbol
Parameter
M48T86
Min
Typ
Max
tCYC
Cycle Time
160
tDSL
Pulse Width, Data Strobe Low or R/W High
80
tDSH
Pulse Width, Data Strobe High or R/W Low
55
tRWH
R/W Hold Time
0
tRWS
R/W Setup Time
10
tCS
Chip Select Setup Time
5
tCH
Chip Select Hold Time
0
tDHR
Read Data Hold Time
0
25
tDHW
Write Data Hold Time
0
tAS
Address Setup Time
20
tAH
Address Hold Time
5
tDAS
Delay Time, Data Strobe to Address Strobe Rise
10
tASW
Pulse Width Address Strobe High
30
tASD
Delay Time, Address Strobe to Data Strobe Rise
35
tOD
Output Data Delay Time from Data Strobe Rise
50
tDW
Write Setup Time
30
tBUC
Delay Time before Update Cycle
244
tPI (1)
Periodic Interrupt Time interval
–
–
–
tUC
Time of Update Cycle
1
Note: 1. See Table 10.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
When an interrupt event occurs, the related flag bit
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is
set to a logic "1". These flag bits are set indepen-
dent of the state of the corresponding enable bit in
Register B and can be used in a polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogate as necessary.
When a flag is set, an indication is given to soft-
ware that an interrupt event has occurred since the
flag bit was last read; however, care should be tak-
en when using the flag bits as all are cleared each
time Register C is read. Double latching is includ-
ed with Register C so that bits which are set, re-
main stable throughout the read cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the read
cycle are held until after the cycle is completed.
One, two, or three bits can be set when reading
Register C. Each utilized flag bit should be exam-
ined when read to ensure that no interrupts are
lost.
The second flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set
and the corresponding enable bit is also set, the
IRQ pin is asserted low. IRQ is asserted as long as
at least one of the three interrupt sources has its
flag and enable bits both set. The IRQF bit (Regis-
ter C; Bit 7) is a "1" whenever the IRQ pin is being
driven low. Determination that the RTC initiated an
interrupt is accomplished by reading Register C.A
logic "1" in the IRQF bit indicates that one or more
interrupts have been initiated by the M48T86. The
act of reading Register C clears all active flag bits
and the IRQF bit.
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