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M48T58Y-70PC1E View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T58Y-70PC1E
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48T58Y-70PC1E Datasheet PDF : 31 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Operation modes
2
Operation modes
M48T58, M48T58Y
Note:
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDEâ„¢ clock information in the bytes with addresses 1FF8h-1FFFh. The clock
locations contain the century, year, month, date, day, hour, minute, and second in 24 hour
BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30,
and 31 day months are made automatically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information and also stores the clock calibration
setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORTâ„¢ READ/write memory cells. The M48T58/Y includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T58/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out-of-tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below the
Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2. Operating modes
Mode
VCC
E1 E2
G
W DQ0-DQ7
Power
Deselect
VIH
X
X
X
Deselect 4.75 to 5.5V
X
VIL
X
X
WRITE
READ
or
4.5 to 5.5V
VIL
VIH
X
VIL
VIL
VIH
VIL
VIH
READ
VIL
VIH
VIH
VIH
Deselect
VSO to VPFD
(min)(1)
X
X
X
X
Deselect
≤ VSO(1)
X
X
X
X
1. See Table 11 on page 23 for details.
High Z
High Z
DIN
DOUT
High Z
High Z
High Z
Standby
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
8/31
 

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