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M48T35-70PC6F View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T35-70PC6F
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48T35-70PC6F Datasheet PDF : 29 Pages
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M48T35 M48T35Y
Operation modes
Table 4. Write mode AC characteristics (continued)
Symbol
Parameter(1)
M48T35/Y
Unit
Min
Max
tWLWH WRITE Enable Pulse Width
50
ns
tELEH Chip Enable Low to Chip Enable High
55
ns
tWHAX WRITE Enable High to Address Transition
0
ns
tEHAX Chip Enable High to Address Transition
0
ns
tDVWH Input Valid to WRITE Enable High
30
ns
tDVEH Input Valid to Chip Enable High
30
ns
tWHDX WRITE Enable High to Input Transition
5
ns
tEHDX Chip Enable High to Input Transition
tWLQZ(2)(3) WRITE Enable Low to Output Hi-Z
5
ns
25
ns
tAVWH Address Valid to WRITE Enable High
60
ns
tAVEH Address Valid to Chip Enable High
60
ns
tWHQX(2)(3) WRITE Enable High to Output Transition
5
ns
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
Data retention mode
With valid VCC applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on
page 19, Table 10, and Table 11 on page 20).
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T35/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)
plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent
WRITE Cycles prior to processor stabilization. Normal RAM operation can resume trec after
VCC exceeds VPFD (max).
For more information on Battery Storage Life refer to the Application Note AN1012.
11/29
 

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