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M41T81SM6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M41T81SM6
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M41T81SM6 Datasheet PDF : 31 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M41T81S
2
Operation
Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Calibration Register
10. Watchdog Register
11 - 15. Alarm Registers
16. Flags Register
17 - 19. Reserved
20. Square Wave Register
The M41T81S clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VPFD, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once VCC falls below the
switchover voltage (VSO), the device automatically switches over to the battery and powers
down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than
VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT. If VBAT is
greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below
VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises
above VPFD, it will recognize the inputs.
For more information on Battery Storage Life refer to Application Note AN1012.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
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