DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M41T81SMY6(2005) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M41T81SMY6
(Rev.:2005)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M41T81SMY6 Datasheet PDF : 29 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
M41T81S
CLOCK OPERATION
The 20-byte Register Map (see Table 2., page 12)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: Tenths/Hundredths of Seconds cannot be
written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Calibration Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
Power-down Timestamp
When a power failure occurs, the HALT (HT) Bit
will automatically be set to a '1.' This will prevent
the clock from updating the TIMEKEEPER® regis-
ters, and will allow the user to read the exact time
of the power-down event. Resetting the HT Bit to
a '0' will allow the clock to update the TIMEKEEP-
ER registers with the current time.
TIMEKEEPER® Registers
The M41T81S offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flags, Square
Wave and Calibration data. These registers are
memory locations which contain external (user ac-
cessible) and internal copies of the data (usually
referred to as BiPORTTIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Calibration, Watchdog and Square Wave
Registers store data in Binary Format.
11/29
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]