M41T60Q6F View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41T60Q6F

Serial access real-time clock

STMicroelectronics 

M41T60

Figure 6. Acknowledgement sequence

START

SCL FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

MSB

DATA OUTPUT

BY RECEIVER

Operation

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

AI00601

2.2

READ mode

In this mode, the master reads the M41T60 slave after setting the slave address

(see Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit,

the word address An is written to the on-chip address pointer. Next the START condition

and slave address are repeated, followed by the READ mode control bit (R/W = 1). At this

point, the master transmitter becomes the master receiver. The data byte which was

addressed will be transmitted and the master receiver will send an acknowledge bit to the

slave transmitter. The address pointer is only increased on reception of an acknowledge bit.

The M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The

master receiver reads and acknowledges the new byte and the address pointer is increased

to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (0h to 6h). The update will resume due to a stop condition or when the

pointer increments to any non-clock address (7h).

An alternate READ mode may also be implemented, whereby the master reads the M41T60

slave without first writing to the (volatile) address pointer. The first address that is read is the

last one stored in the pointer (see Figure 9 on page 10).

Figure 7. Slave address location

R/W

START

SLAVE ADDRESS

A

11 01 0 0 0

AI00602

Doc ID 10396 Rev 13

9/27

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