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M41ST85YMX6TR View Datasheet(PDF) - STMicroelectronics

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M41ST85YMX6TR Datasheet PDF : 34 Pages
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Figure 13. Alternate READ Mode Sequence
M41ST85Y, M41ST85W
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 14., page 11. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
Figure 14. WRITE Mode Sequence
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
11., page 10) and again after it has received the
word address and each data byte.
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
DATA n
DATA n+1
DATA n+X P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
11/34
 

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