M41ST84WMQ6E_06 View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
M41ST84WMQ6E_06 Datasheet PDF : 29 Pages
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Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
SCL
P
tHD:STA
tR
tF
tHIGH
S
tLOW
tSU:DAT
tHD:DAT
M41ST84W
tHD:STA
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can start
1.3
µs
tF
SDA and SCL Fall Time
300
ns
tHD:DAT(2)
Data Hold Time
0
µs
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tR
SDA and SCL Rise Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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