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M36W0R6040B0 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M36W0R6040B0 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package ST-Microelectronics
STMicroelectronics ST-Microelectronics
M36W0R6040B0 Datasheet PDF : 18 Pages
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M36W0R6040T0, M36W0R6040B0
Table 2. Main Operating Modes
Operation
EF GP WP LF RPF WAITF(4) E1P E2P GP WP UBP LBP DQ15-DQ0
Flash Read
VIL VIL VIH VIL(2) VIH
Flash Data Out
Flash Write
Flash Address
Latch
VIL VIH VIL VIL(2) VIH
VIL X VIH VIL VIH
PSRAM must be disabled
Flash Data In
Flash Data Out
or Hi-Z (3)
Flash Output
Disable
VIL VIH VIH X VIH
Flash Standby VIH X X X VIH
Hi-Z
Any PSRAM mode is allowed
Flash Hi-Z
Flash Hi-Z
Flash Reset
XXX
X VIL
Hi-Z
Flash Hi-Z
PSRAM Read
PSRAM Write
Flash Memory must be disabled
VIL VIH VIL VIH VIL VIL
PSRAM data
out
VIL VIH VIH VIL VIL VIL PSRAM data in
Output Disable
VIL VIH VIH VIH X X PSRAM Hi-Z
PSRAM
Standby
Any Flash mode is allowed.
VIH VIH X X X X PSRAM Hi-Z
PSRAM Deep
Power-Down
X VIL X X X X PSRAM Hi-Z
Note: 1. X = Don't care.
2. LF can be tied to VIH if the valid address has been previously latched.
3. Depends on GF.
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064F(T/B) datasheet for details.
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