See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). Addresses A0-A19
are common inputs for the Flash Memory and
PSRAM components. The Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the commands sent to the Command
Interface of the Flash memory Program/Erase
Controller, and they select the cells to access in
The Flash memory is accessed through the Chip
Enable signal (EF) and through the Write Enable
(WF) signal, while the PSRAM is accessed through
two Chip Enable signals (E1P and E2P) and the
Write Enable signal (WP).
Address Inputs (A20-A21). Addresses A20-A21
are inputs for the Flash memory component only.
The Flash memory is accessed through the Chip
Enable signals (EF) and through the Write Enable
Data Input/Output (DQ0-DQ15). For the Flash
memory, the Data I/O outputs the data stored at
the selected address during a Bus Read operation
or inputs a command or the data to be pro-
grammed during a Write Bus operation.
For the PSRAM, the Upper Byte Data Inputs/Out-
puts carry the data to or from the upper part of the
selected address during a Write or Read opera-
tion, when Upper Byte Enable (UBP) is driven Low.
Likewise, the Lower Byte Data Inputs/Outputs car-
ry the data to or from the lower part of the selected
address during a Write or Read operation, when
Lower Byte Enable (LBP) is driven Low.
Flash Chip Enable (EF). The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, VIL, and Reset is High, VIH, the de-
vice is in active mode. When Chip Enable is at VIH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (GF). The Output Enable
pins control data outputs during Flash memory
Bus Read operations.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 7., Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at VIH or Flash Reset is at VIL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enable.
PSRAM Chip Enable (E1P). When asserted
(Low), the Chip Enable, E1P, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2P). The Chip Enable,
E2P, puts the device in Deep Power-down mode
when it is driven Low. This is the lowest power