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M36W216 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M36W216 16 Mbit 1Mb x16 / Boot Block Flash Memory and 2 Mbit 128Kb x16 SRAM / Multiple Memory Product ST-Microelectronics
STMicroelectronics ST-Microelectronics
M36W216 Datasheet PDF : 62 Pages
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M36W216TI, M36W216BI
The M36W216TI contains one 16 Mbit Flash
memory. This section describes how to use the
Flash device and all signals refer to the Flash de-
The Flash Memory is a 16 Mbit (1 Mbit x 16) non-
volatile device that can be erased electrically at
the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. VDDQF is used to drive the I/O pin down to
1.65V. An optional 12V VPPF power supply is pro-
vided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture with an array of 39 blocks: 8 Parameter
Blocks of 4 KWords and 31 Main Blocks of 32
KWords. The M36W216TI has the Parameter
Blocks at the top of the memory address space
while the M36W216BI locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 10, Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPPF VPPLK all blocks are protected
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divid-
ed into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the us-
er. The user programmable segment can be per-
manently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 11, shows the Flash Security
Block Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
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