M29W800DB70M1E View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

Manufacturer

M29W800DB70M1E

8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block) 3 V supply flash memory

Numonyx -> Micron 

M29W800DT, M29W800DB

Command interface

4.7

Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six bus write operations are

required to issue the Chip Erase command and start the program/erase controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all

of the blocks are protected the chip erase operation appears to start but will terminate within

about 100 µs, leaving the data unchanged. No error condition is given when protected

blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue

any command to abort the operation. Typical chip erase times are given in Table 6: Program,

erase times and program, erase endurance cycles. All bus read operations during the chip

erase operation will output the status register on the data inputs/outputs. See the Section 5:

Status register for more details.

After the chip erase operation has completed the memory will return to the read mode,

unless an error has occurred. When an error occurs the memory will continue to output the

status register. A Read/Reset command must be issued to reset the error condition and

return to read mode.

The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All

previous data is lost.

4.8

Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. Six bus write

operations are required to select the first block in the list. Each additional block in the list can

be selected by repeating the sixth bus write operation using the address of the additional

block. The block erase operation starts the program/erase controller about 50 µs after the

last bus write operation. Once the program/erase controller starts it is not possible to select

any more blocks. Each additional block must therefore be selected within 50 µs of the last

block. The 50 µs timer restarts when an additional block is selected. The status register can

be read after the sixth bus write operation. See the status register for details on how to

identify if the program/erase controller has started the block erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks

are erased. If all of the selected blocks are protected the block erase operation appears to

start but will terminate within about 100 µs, leaving the data unchanged. No error condition

is given when protected blocks are ignored.

During the block erase operation the memory will ignore all commands except the Erase

Suspend command. Typical block erase times are given in Table 6: Program, erase times

and program, erase endurance cycles. All bus read operations during the block erase

operation will output the status register on the data inputs/outputs. See the Section 5: Status

register for more details.

After the block erase operation has completed the memory will return to the read mode,

unless an error has occurred. When an error occurs the memory will continue to output the

status register. A Read/Reset command must be issued to reset the error condition and

return to read mode.

The Block Erase command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

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