There are five standard bus operations that control the device. These are bus read, bus
write, output disable, standby and automatic standby. See Table 2 and Table 3, Bus
operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus read operations read from the memory cells, or specific registers in the command
interface. A valid bus read operation involves setting the desired address on the address
inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The data inputs/outputs will output the value, see Figure 11: Read mode
AC waveforms, and Figure 12: Read AC characteristics for details of when the output
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole bus write operation. See Figure 12 and Figure 13, Write AC waveforms,
and Table 13 and Table 14, Write AC characteristics, for details of the timing requirements.
The data inputs/outputs are in the high impedance state when Output Enable is High, VIH.
When Chip Enable is High, VIH, the memory enters standby mode and the data
inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to
the standby supply current, ICC2, Chip Enable should be held within VCC ± 0.2 V. For the
standby current level see Table 11: DC characteristics.
During program or erase operations the memory will continue to use the program/erase
supply current, ICC3, for program or erase operations until the operation completes.
If CMOS levels (VCC ± 0.2 V) are used to drive the bus and the bus is inactive for 150 ns or
more the memory enters automatic standby where the internal supply current is reduced to
the standby supply current, ICC2. The data inputs/outputs will still output data if a bus read
operation is in progress.