EDD5104ABTA-6B View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EDD5104ABTA-6B

512M bits DDR SDRAM

Elpida Memory, Inc 

EDD5104ABTA, EDD5108ABTA

Operation of the DDR SDRAM

Power-up Sequence

The following sequence is recommended for Power-up.

(1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined).

Apply VDD before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and VREF.

(2) Start clock and maintain stable condition for a minimum of 200 µs.

(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.

(4) Issue precharge all command for the device.

(5) Issue EMRS to enable DLL.

(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of

clock input is required to lock the DLL after every DLL reset).

(7) Issue precharge all command for the device.

(8) Issue 2 or more auto-refresh commands.

(9) Issue a mode register set command to initialize device operation.

/CK

CK

Command

PALL

EMRS

MRS

PALL

RERFEF

REF

2 cycles (min.) 2 cycles (min.) 2 cycles (min.)

tRP

tRFC

DLL enable

DLL reset

200 cycles (min)

Power-up Sequence after CKE Goes High

MRS

Any

command

tRFC

2 cycles (min.)

Mode Register and Extended Mode Register Set

There are two mode registers, the mode register and the extended mode register so as to define the operating

mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command

[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are

set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine

which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode

register must be set.

Remind that no other parameters are shown in the table bellow are allowed to input to the registers.

BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 DR 0

LMODE BT

BL

MRS

A8 DLL Reset

0 No

1 Yes

A6 A5 A4 CAS Latency

010

2

110

2.5

A3 Burst Type

0 Sequential

1 Interleave

Burst Length

A2 A1 A0

BT=0 BT=1

0 01 2 2

0 10 4 4

0 11 8 8

Mode Register Set [MRS] (BA0 = 0, BA1 = 0)

Preliminary Data Sheet E0237E30 (Ver. 3.0)

22

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