EDD5108ABTA-6B View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EDD5108ABTA-6B

512M bits DDR SDRAM

Elpida Memory, Inc 

EDD5104ABTA, EDD5108ABTA

Auto-refresh command [REF]

This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined

by the internal refresh controller. The average refresh cycle is 7.8 µs. The output buffer becomes High-Z after auto-

refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can

be issued tRFC after the last auto-refresh command.

Self-refresh entry [SELF]

This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-

refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is

terminated by a self-refresh exit command.

Power down mode entry [PDEN]

tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In

power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode

continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not

disable DLL.

Self-refresh exit [SELFX]

This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.

((tSNR =)10 cycles for tCK = 7.5 ns or 12 cycles for tCK = 6.0 ns after [SELFX]) To issue read command, tSRD has

to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command

within 7.8 µs.

Power down exit [PDEX]

The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.

Preliminary Data Sheet E0237E30 (Ver. 3.0)

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