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M24C32FCS6GA View Datasheet(PDF) - STMicroelectronics

Part NameM24C32FCS6GA ST-Microelectronics
STMicroelectronics ST-Microelectronics
Description128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM
M24C32FCS6GA Datasheet PDF : 39 Pages
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Description
1
Description
M24128, M24C64, M24C32
The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable
programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits
and 16384 × 8 bits, respectively.
Figure 1. Logic diagram
VCC
3
E0-E2
SCL
WC
M24128
M24C64
M24C32
SDA
VSS
AI01844e
I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I2C bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
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